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74AHC30; 74AHCT30
8-input NAND gate
Rev. 03 -- 26 June 2009 Product data sheet
1. General description
The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC30; 74AHCT30 provides an 8-input NAND function.
2. Features
I I I I Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: N For 74AHC30: CMOS level N For 74AHCT30: TTL level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from -40 C to +85 C and from -40 C to +125 C
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74AHC30D 74AHCT30D 74AHC30PW 74AHCT30PW 74AHC30BQ 74AHCT30BQ -40 C to +125 C DHVQFN14 -40 C to +125 C TSSOP14 -40 C to +125 C SO14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 Type number
plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
4. Functional diagram
1 2 3 4 5 6 11 12
A B C D E F G H
mna488
1 2 3 Y 8 4 5 6 11 12
&
8
mna489
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
A B C D Y E
mna490
F G H
Fig 3.
Logic diagram
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
2 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
5. Pinning information
5.1 Pinning
74AHC30 74AHCT30 74AHC30 74AHCT30
A B C D E F GND 1 2 3 4 5 6 7
001aai162
terminal 1 index area B 14 VCC 13 n.c. 12 H 11 G 10 n.c. 9 8 n.c. Y F 6 C D E 2 3 4 5
14 VCC 13 n.c. 12 H 11 G 10 n.c. 9 n.c. Y 8
GND(1) 7 GND
1
A
001aak237
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2. Symbol A B C D E F GND Y n.c. n.c. G H n.c. VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description data input data input data input data input data input data input ground (0 V) data output not connected not connected data input data input not connected supply voltage
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
3 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
6. Functional description
Table 3. Input A L X X X X X X X H
[1]
Function table[1] Output B X L X X X X X X H C X X L X X X X X H D X X X L X X X X H E X X X X L X X X H F X X X X X L X X H G X X X X X X L X H H X X X X X X X L H Y H H H H H H H H L
H = HIGH voltage level; L = LOW voltage level; X = don't care.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot
[1] [2]
Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation
Conditions
Min -0.5 -0.5
Max +7.0 +7.0 +20 +25 +75 +150 500
Unit V V mA mA mA mA mA C mW
VI < -0.5 V VO < -0.5 V or VO > VCC + 0.5 V VO = -0.5 V to (VCC + 0.5 V)
[1] [1]
-20 -20 -25 -75 -65
Tamb = -40 C to +125 C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO14 packages: above 70 C the value of Ptot derates linearly at 8 mW/K. For TSSOP14 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN14 packages: above 60 C the value of Ptot derates linearly at 4.5 mW/K.
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
4 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
8. Recommended operating conditions
Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb t/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V Conditions Min 2.0 0 0 -40 74AHC30 Typ 5.0 +25 Max 5.5 5.5 VCC +125 100 20 Min 4.5 0 0 -40 74AHCT30 Typ 5.0 +25 Max 5.5 5.5 VCC +125 20 V V V C ns/V ns/V Unit
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC30 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = -50 A; VCC = 2.0 V IO = -50 A; VCC = 3.0 V IO = -50 A; VCC = 4.5 V IO = -4.0 mA; VCC = 3.0 V IO = -8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V IO = 50 A; VCC = 3.0 V IO = 50 A; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V II ICC CI input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 0 0 0 3 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 0.1 2.0 10 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.80 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 1.0 20 10 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 2.0 40 10 V V V V V V V V V V V V V V V V A A pF Conditions Min 25 C Typ Max -40 C to +85 C -40 C to +125 C Unit Min Max Min Max
supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance VI = VCC or GND
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
5 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CO output capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V Conditions Min 25 C Typ 4 Max -40 C to +85 C -40 C to +125 C Unit Min Max Min Max pF
74AHCT30 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V
HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = -50 A IO = -8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V
4.4 3.94 -
4.5 0 -
0.1 0.36 0.1 2.0 1.35
4.4 3.80 -
0.1 0.44 1.0 20 1.5
4.4 3.70 -
0.1 0.55 2.0 40 1.5
V V V V A A mA
VOL
II ICC ICC
supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V input capacitance output capacitance VI = VCC or GND
CI CO
-
3 4
10 -
-
10 -
-
10 -
pF pF
10. Dynamic characteristics
Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 74AHC30 tpd propagation A, B, C, D, E, F, G, H to Y; delay see Figure 6 and 7 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF 3.6 4.9 6.5 8.0 1.0 1.0 7.5 9.5 1.0 1.0 8.0 10.5 ns ns 5.0 6.7 9.5 12.0 1.0 1.0 11.0 14.5 1.0 1.0 12.0 15.5 ns ns
[2]
Conditions
25 C Min Typ[1] Max
-40 C to +85 C Min Max
-40 C to +125 C Unit Min Max
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
6 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter CPD Conditions Min fi = 1 MHz; power dissipation VI = GND to VCC capacitance propagation A, B, C, D, E, F, G, H to Y; delay see Figure 6 and 7 CL = 15 pF CL = 50 pF CPD power fi = 1 MHz; dissipation VI = GND to VCC capacitance
[3] [3]
25 C Typ[1] 10 Max -
-40 C to +85 C Min Max -
-40 C to +125 C Unit Min Max pF
74AHCT30; VCC = 4.5 V to 5.5 V tpd
[2]
-
3.3 4.7 12
6.5 8.5 -
1.0 1.0 -
7.5 9.5 -
1.0 1.0 -
8.0 10.5 -
ns ns pF
[1] [2] [3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs.
11. Waveforms
VI A, B, C, D, E, F, G, H input GND
VM
tPHL VOH Y output VOL VM
tPLH
mna491
Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Table 8. Type 74AHC30
Input to output propagation delays Measurement points Input VM 0.5 x VCC 1.5 V Output VM 0.5 x VCC 0.5 x VCC
74AHCT30
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
7 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
VI negative pulse GND
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VCC G
VI VO
VM
VI positive pulse GND
VM
DUT
RT CL
001aah768
Test data is given in Table 9. Definitions for test circuit: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance.
Fig 7. Table 9. Type 74AHC30
Load circuitry for measuring switching times Test data Input VI VCC 3.0 V tr, tf 3.0 ns 3.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF tPLH, tPHL tPLH, tPHL Test
74AHCT30
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
8 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 pin 1 index Lp 1 e bp 7 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 8.
Package outline SOT108-1 (SO14)
(c) NXP B.V. 2009. All rights reserved.
74AHC_AHCT30_3
Product data sheet
Rev. 03 -- 26 June 2009
9 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 9.
Package outline SOT402-1 (TSSOP14)
(c) NXP B.V. 2009. All rights reserved.
74AHC_AHCT30_3
Product data sheet
Rev. 03 -- 26 June 2009
10 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 6 vMCAB wM C y1 C
C y
1 Eh 14
7 e 8
13 Dh 0
9 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 10. Package outline SOT762-1 (DHVQFN14)
74AHC_AHCT30_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
11 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
13. Abbreviations
Table 10. Acronym CDM CMOS DUT ESD HBM LSTTL MM Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model
14. Revision history
Table 11. Revision history Release date 20090626 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT30_2 Document ID 74AHC_AHCT30_3 Modifications:
* * *
Section 3: DHVQFN14 package added. Section 7: derating values added for DHVQFN14 package. Section 12: outline drawing added for DHVQFN14 package. Product data sheet Product specification 74AHC_AHCT30_1 -
74AHC_AHCT30_2 74AHC_AHCT30_1
20080530 19991130
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
12 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT30_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 26 June 2009
13 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 June 2009 Document identifier: 74AHC_AHCT30_3

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